Proper termination of high-frequency signals are of particular concern in the design and implementation of electronic circuits, such as digital computers, microprocessors, digital signal processors, memory circuits, or virtually any other electronic circuit in which impedance matching of a receiving or transmitting circuit coupled to a transmission line is important. Indeed, if the impedance of a receiving or transmitting circuit is not properly controlled, then undesired transmission line effects may result, such as undesirable signal reflections. Signal reflections are of particular concern in high-frequency applications when the transmission line delay becomes comparable to, or exceeds, the waveform transition times of the transmitted signals. This obtains particularly in high speed digital circuits, where signal reflections may result in unwanted interference with an incident or received signal that in turn results in an erroneous logic level.
Transmission lines are described generally by a characteristic impedance, frequently in the range of 30 to 120 ohms. The characteristic impedance typically depends on the geometric properties of the line, the dielectric permittivity, and the magnetic permeability of the insulating material, and by a signal transmission delay proportional to line length. The characteristic impedance is the ratio of voltage to current of transmitted waveforms that propagate down the line. When the line is terminated in a resistance reasonably close to its characteristic impedance, no substantial waveform reflection occurs. When there is a substantial impedance mismatch, voltage overshoots associated with waveform reflection are generally produced that provide a disadvantageous mechanism for corruption of logic signals.
A prior art technique of providing termination of a transmission line with a desirable impedance is illustrated in FIG. 1. In particular, FIG. 1 illustrates a termination circuit 10 providing a termination node DQ, including a resistor divider comprising a first resistor RA and a second resistor RB coupled in series across voltage sources Vdd and Vss. The termination circuit is coupled to a main circuit 11 that is operable to perform one or more functions such as performed by microprocessors, digital signal processors, memory circuits, or other general signal processing devices. For illustrative purposes, the main circuit 11 might include an I/O buffer 12 that performs a signal isolation or conditioning function, coupled to a functional circuit 13. The termination circuit 10 is coupled to the main circuit 11 by a transmission line TL, recognizing the physical separation between these two circuits. The transmission line TL is described by a characteristic impedance and a transmission delay.
With the configuration shown for the termination circuit 10, the impedance at the termination node DQ is approximately equal to the parallel combination of resistors RA and RB. The values of RA and RB are selected to achieve a line termination impedance substantially equal to the transmission line characteristic impedance, thereby reducing or eliminating unwanted signal reflections. Among the disadvantages of this prior art resistor-termination approach are relatively high cross currents through the resistors RA and RB as a consequence of the dc voltage difference between the nodes Vdd and Vss, and attendant power dissipation.
Power consumption and dissipation characteristics of the resistor-termination approach will be discussed with reference to FIG. 2. FIG. 2 illustrates the current and voltage characteristics of the respective resistors RA and RB. The voltage VDQ along the abscissa of the illustrated graph represents a voltage induced on the termination node DQ of the termination circuit 10 of FIG. 1. The induced voltage may be produced by the I/O buffer 12 on FIG. 1 or a driver circuit (e.g., from another integrated circuit) that operates to produce a logic high level or a logic low level. For example, the driver circuit might output a logic high level by placing a voltage approaching Vdd on the termination node DQ. Alternatively, the driver circuit might operate to produce a logic low level by placing a voltage approaching Vss on the termination node DQ.
The voltage placed on the termination node DQ by the driver circuit affects the current in the resistors RA and RB. Assuming that RA and RB are substantially equal to one another, then the currents IRA and IRB through RA and RB, respectively, intersect one another at a termination node DQ voltage of about             Vdd      +      Vss        2    ,which represents the quiescent current in the resistors RA and RB, i.e., when no current flows into the termination node DQ. If the resistors RA and RB are each equal to twice the characteristic impedance of the coupled transmission line, then the impedance of the termination node DQ will be equal to the parallel combination of the resistance of RA and RB, which is desirably the transmission line characteristic impedance. The resulting quiescent current through resistors RA and RB when no current flows into the termination node DQ will be one quarter the potential difference between the voltage sources Vdd and Vss divided by the transmission line characteristic impedance. In practice to maintain sufficient signal integrity, it is generally not required to match precisely the transmission line characteristic impedance with a termination impedance. Often the termination impedance is set somewhat higher than the line characteristic impedance to reduce power dissipation in the termination circuit.
As the voltage VDQ at the termination node DQ is reduced by the driver circuit, the current IRA through resistor RA increases (due to an increase in the voltage thereacross) and the current IRB through resistor RB decreases (due to a reduction in the voltage thereacross). Depending on the specific values of Vdd, Vss, RA, and RB, the magnitude of the currents IRA and IRB may be several mA (e.g., about 5–10 mA) for an exemplary potential difference between Vdd and Vss of 1.8 volts and a transmission line characteristic impedance of 75 ohms. This is a relatively high value, and represents substantial power dissipation for a small, integrated signaling circuit with many I/O lines, particularly when the signal transmission function may be idle for a substantial fraction of the time. The circuit in FIG. 1 does not provide the capability to selectively disable or decouple the termination function when it is known that no signal is being transmitted. By this means the power associated with quiescent current flow in the termination resistors would be saved entirely.
Other prior art techniques provide a clamp termination circuit that limits the voltage excursion of the termination node DQ not to be substantially greater than the voltage source Vdd and not substantially less than the voltage source Vss. While often providing protection for the receiving logic coupled to the termination node DQ, significant voltage waveform reflections in the transmission line are generally created by the non-linear characteristics of the clamp circuit, transferring the transmission line termination problem to its opposite end.
Accordingly, there are needs in the art for new methods and apparatus for terminating a signal that do not draw excessive current from a power supply, yet provide a controlled impedance in order to reduce or eliminate signal reflections, or a clamping function to limit voltage overshoots.